The present invention relates generally to CMOS device fabrication processes and, more particularly, to a method of manufacturing amorphous high dielectric constant film devices that are subject to oxidation processes at temperatures whereby crystallization of the amorphous high dielectric constant film is avoided.
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide, is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors and interconnects, which have less than 1.0 micron critical dimension. As feature size decreases, the size of the resulting transistor as well as the interconnect between transistors also decreases. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
In semiconductor device fabrication, polysilicon and silicon dioxide are commonly used to form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. As device dimensions have continued to scale down, the thickness of the SiO2 layer has also decreased to maintain the same capacitance between the gate and channel regions. A thickness of the gate oxide layer of less than 2 nanometers (nm) is expected in the future.
In order to achieve increased capacitance, gate oxide thickness has been reduced so much that current oxides are on the order of ten angstroms (1 nm) thick. Unfortunately, thin oxide films may break down when subjected to an electric field, particularly for gate oxides less than 50 Angstroms thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through a thin gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that some of these electrons may become entrapped within the gate oxide by e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, the threshold voltage VT may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of gate voltage, as a result of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice.
Because of high direct tunneling currents, SiO2 films thinner than 1.5 nm cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts to replace SiO2 with high-k dielectrics, with TiO2 and Ta2 O5 attracting the greatest attention. However, high temperature post deposition annealing treatments in the presence of oxygen to clean the film by oxidation of impurities and to fill oxygen vacancy defects (form oxide films) in the films (form oxide films) has been found to detrimentally affect high-k dielectric films by leading to crystallization of the film and formation of an interfacial SiO2 layer during the annealing treatment, make achieving an equivalent SiO2 thickness (EOT) of less than 1.5 nm very difficult. As will be appreciated, the high temperature oxygen anneal can cause oxygen to diffuse through the dielectric and form undesired silicon dioxide at the metal oxide/silicon nitride and/or at the silicon nitride/poly interfaces. Silicon dioxide formation at these interfaces will create a low dielectric constant film in series with the high dielectric metal oxide film and therefore reduce the effective capacitance of the film.
One solution to lowering the high tunneling current through thin gate oxide layers (typically SiO2) has been to use alternative high dielectric constant gate oxide materials. Materials with high dielectric constants permit gate dielectric layers to be made thicker, and so alleviate the tunneling current problem. While silicon dioxide (SiO2) has a dielectric constant of approximately 4, other materials have higher k (dielectric constant) values. Silicon nitride (xe2x80x9cnitridexe2x80x9d), for example, has a k of about 6 to 9 (depending on formation conditions). Much higher dielectric constant values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta2O5), barium strontium titanate (xe2x80x9cBSTxe2x80x9d), and lead zirconate titanate (xe2x80x9cPZTxe2x80x9d). Using a high-k material for a gate dielectric would allow a high capacitance to be achieved even with a relatively thick dielectric. For example, a nitride gate dielectric having a thickness of 100 angstroms is substantially electrically equivalent to a silicon oxide gate dielectric having a thickness of about 50 angstroms. For even higher-k dielectrics, even thicker gate dielectrics could be formed while maintaining capacitance values higher than are possible with even very thin oxide layers. In this way, the reliability problems associated with very thin dielectric layers may be avoided while transistor performance is increased. These high-k dielectric films (high dielectric constant films) are defined herein as having a high dielectric constant relative to silicon dioxide. Typically, silicon dioxide has a dielectric constant of approximately 3.9, while high dielectric constant films have dielectric constants in the range of about 20 to 40.
Another problem associated with the above-mentioned high-k dielectrics is that, as mentioned, they may develop a crystalline structure under normal preparation conditions leading to a roughened film surface. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
Despite their advantages, high-k materials pose IC fabrication challenges. For example, high-k material is relatively difficult to etch, unlike a conventional thermal oxide. Chemical etchants used with high-k materials may cause increased damage to associated oxide materials making high temperature rapid thermal oxidation processes necessary to repair such damage while leading to the undesirable effect of crystallization of an amorphous high-k dielectric film.
As a result, it would be advantageous if high-k dielectric films could be formed with reduced surface roughness, crystallinity, and electrical leakage. It would be advantageous if these non-crystalline high dielectric constant materials could be used in gate dielectrics and storage capacitors of integrated circuits. Possible solutions are to improve the thermal stability of the high-k dielectric films thereby avoiding film crystallization, or to provide processes whereby lower process temperatures (lower thermal budgets) are achieved. The thermal budget of a process is defined as the integral of device temperature T (t) over a fixed period of time.
High temperature processes that may be typically included in CMOS device manufacture include LDD (lightly doped drain) processes carried out at temperatures greater or equal to 900xc2x0 C. and S/D (source/drain) activation carried out at greater or equal to 1000xc2x0 C. More importantly, other processes may degrade high-k dielectric film properties such as poly-gate oxidation carried out at temperatures of about 1000xc2x0 C.
Therefore it would be advantageous to develop a low temperature oxidation process whereby high-k dielectric film properties are not degraded. It is therefore an object of the invention to provide a low temperature oxidation process with a low thermal budget to carry out oxidations, thereby solving the problem of high-k dielectric film degradation in small structure (e.g., 0.10 micron) devices.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for carrying out carrying out a low temperature ozone enhanced oxidation process of a high dielectric constant film.
In one embodiment, the present invention provides a low temperature oxidation process of a high dielectric constant film including: providing a semiconductor device comprising an amorphous high dielectric constant film deposited on a substrate; heating the amorphous high dielectric constant film in the presence of an ozone containing ambient to a temperature below which the amorphous high dielectric constant film begins to crystallize; and, forming an oxide film over the semiconductor device.
In a related embodiment, the present invention includes heating the amorphous high dielectric constant film over a range of temperatures from about 450xc2x0 C. to about 550xc2x0 C.
In another related embodiment, the ozone containing ambient may include a mixture of at least ozone and oxygen and the ozone concentration may be varied to alter the rate of the oxide film growth over the semiconductor device. In particular, changing the ozone concentration will cause the growth rate of the oxide film to vary in direct proportion thereto.
In yet another related embodiment, the temperature of the ambient may be varied to alter the growth rate of the oxide film over the semiconductor device. In particular, changing the temperature will cause the growth rate of the oxide film to vary in direct proportion thereto.
In yet another related embodiment, the low temperature ozone enhanced oxidation process follows a wet chemical etching process where the chemicals may include the use of HF and hot H3PO4, and where the low temperature ozone enhanced oxidation replaces a relatively higher temperature rapid thermal oxidation process where crystallization of the amorphous high dielectric constant film may occur. In this embodiment, the low temperature ozone enhanced oxidation process is carried out at a temperature and a period of time such that an etching damage is removed and crystallization of the amorphous high dielectric constant film is avoided.
In yet another related embodiment, the method of the present invention replaces a process of the prior art including a high temperature poly-gate oxidation.
In yet another related embodiment, the method of the present invention is carried out at a temperature and a period of time such that formation of an interfacial oxide layer is avoided.
In yet another embodiment, according to the present invention, includes a method for carrying out a low temperature enhanced ozone oxidation process on a front end gate dielectric device including: providing a front end gate dielectric device comprising an amorphous high dielectric constant film; and, heating the amorphous high dielectric constant film in the presence of an ozone containing ambient to a temperature for a period of time such that crystallization of the amorphous high dielectric constant is avoided.